1. Technical Filed of the Invention
The present invention relates to semiconductor devices with a structure having multiple wiring layers, and more particularly to semiconductor devices with a structure having multiple wiring layers including dummy wirings.
2. Background Technology
At present, wiring layers are formed in multiple layers in semiconductor devices in order to achieve a higher integration and further miniaturization. An interlayer dielectric layer is formed between one wiring layer and another wiring layer formed above that wiring layer. The interlayer dielectric layer is planarized by a chemical mechanical polishing method (CMP method).
A technique has been proposed to improve the flatness of the interlayer dielectric layer. According to this technique, as shown in FIGS. 7 and 8, dummy wirings 130 are formed between densely formed wiring layers 170 and an isolated wiring layer 171 in the same wiring layer level and in the same steps to form these wiring layers. FIG. 7 shows a plan view of a semiconductor device having a structure with multiple wiring layers, and FIG. 8 schematically shows a cross section taken along a line Bxe2x80x94B in the semiconductor device shown in FIG. 7. FIG. 7 shows a plan view of the device when it is cut along a plane including the bonding pad 14 and in parallel with a surface of a silicon substrate 111 shown in FIG. 8. As indicated in FIGS. 7 and 8, the dummy wirings 130 thus formed can prevent interlayer dielectric layers 110a-110f from creating step differences between them.
Bonding pads are normally formed to electrically connect external electrodes of the semiconductor device and elements within the semiconductor device. For example, in the semiconductor device shown in FIGS. 7 and 8, a bonding pad 140 is formed in a layer at the same level as that of the dummy wirings 130 that are formed in the uppermost layer. The bonding pad 140 is connected to an electrode (not shown) outside the semiconductor device through, for example, a bump electrode (not shown). Furthermore, as shown in FIG. 8, dummy wirings 150 are also formed in layers at levels lower than that of the dummy wirings 130 and the bonding pad 140 in order to improve the flatness of the interlayer dielectric layers. For example, Japanese laid-open patent application HEI 10-335333 describes a semiconductor device having such a structure.
However, when the semiconductor device includes the dummy wirings 150 that are formed in a region immediately below the bonding pad 140, the following problems may occur when the bonding pad 140 and an electrode outside of the semiconductor device are to be electrically connected through a bump electrode.
Due to a pressure applied to the surface of the bonding pad 140 at the time of bonding, the dummy wirings 150 that are formed immediately below the bonding pad 140 are compressed by the interlayer dielectric layers 110a-110e formed above and below the dummy wirings 150, and may deform.
The dummy wirings 150 may exfoliate from the interlayer dielectric layers 110a-110e, which may cause a bonding exfoliation.
It is an object of the present invention to provide a semiconductor device with a structure having multiple wiring layers including dummy wirings, which provides good yield.
(Semiconductor Device) A semiconductor device in accordance with the present invention includes multiple wiring layers and a bonding pad, and the semiconductor device comprises:
a dummy wiring forming region where dummy wirings are formed; and
a dummy wiring prohibiting region where the dummy wirings are not formed,
wherein at least the bonding pad and an area immediately below the bonding pad define the dummy wiring prohibiting region.
It is noted that bonding pads are, among metal wiring layers, exposed surfaces in the metal wiring layers, which are exposed through openings formed in a dielectric layer such as a protection film, in order to electrically connect external electrodes of a semiconductor device and internal elements of the semiconductor device.
In accordance with the present invention, at least the bonding pad and an area immediately below the bonding pad are defined as the dummy wiring prohibiting region, such that dummy wirings are not provided immediately below the bonding pad, and therefore the dummy wirings do not exfoliate, and bonding exfoliation does not occur. As a result, devices with good yield can be manufactured.
The following examples are preferred embodiments of the semiconductor device in accordance with the present invention.
The dummy wiring pattern can be defined as an area that is expanded by a specified distance in parallel with the bonding pad from an outer circumference of the bonding pad and an outer circumference of the area immediately below the bonding pads. In this case, the specified distance may preferably be 4-15 xcexcm.
The semiconductor device may further include a scribe region, wherein the scribe region is the dummy wiring prohibiting region. This structure can prevent short circuits that may be caused by the dummy wirings which are exfoliated in a dicing process.
A dummy wiring forming region identification mark, a package assembly alignment mark, a chip-interior name indication, a reticle accuracy measuring mark, a product identification number indication, a repair alignment mark, and a fuse may be provided in the dummy wiring prohibiting region. According to this structure, when the dummy wiring prohibiting region is provided in the area described above, the marks and indications can be reliably identified.